1. Field of the Invention
The present invention relates generally to the manufacture of semiconductor MOS devices. More particularly, the present invention relates to a high-voltage semiconductor MOS making process that is compatible with low-voltage semiconductor MOS making process.
2. Description of the Prior Art
Integrated circuits (ICs) containing both high-voltage and low-voltage devices such as high/low voltage MOS transistor devices are known in the art. For example, the low-voltage device may be used in the control circuits as the high-voltage device may be used in electrically programmable read only memory (EPROM) or the driving circuits of the liquid crystal display.
Isolation structures such as field oxide layers, which increase the distance between the gate and the source/drain and further decrease the transverse electric field in the channel, are used for preventing short channel effects of the high-voltage MOS device. Thus, the high-voltage MOS transistor devices can function during high-voltage (30V˜40V) operations.
Hitherto, for the ICs having both high-voltage and low-voltage devices, the production process applied for the low-voltage device is still limited to 0.5 to 0.6 micron technologies. However, in order to increase the integrity of the ICs, it is necessary to introduce more advanced technology, for instance, below 0.35-micron technology. Inevitably, complex anti-punch-through doping or multistep well doping must be applied to produce a low-voltage device in such a small size to adjust the electrical properties of the device, and to prevent the punch-through problems that occur in the low-voltage device.
In addition to increasingly complex process steps for high/low voltage devices, there are some other drawbacks when applying prior art 40V high-voltage process in combination with advanced 3.3V low-voltage process. First, severe field oxide encroachment under SiN leads to control problems of length and width of the active areas in the low-voltage device region. This is because the formation of the post-implant oxide for both high-voltage N-well (HVNW) and the high-voltage P-well (HVPW), thermal drive-in for the HVNW and the HVPW, and removal of the post-implant oxide are executed after the SiN definition of active area.
Secondly, formation and removal of the sacrificial oxide layer during the drive-in step for the grade doping regions (parts of source/drain regions of high-voltage devices) in the high-voltage device area lead to field oxide edge thinning, and thus adversely affecting low-voltage devices. Serious kink effects are observed when operating the low-voltage devices.
Further, in accordance with the prior art method, the field doping layers in the high-voltage device area, which function as a channel stop, are implanted into the substrate prior to the formation of field oxide layers. This is disadvantageous because the dopants in the field doping layers will laterally diffuse when taking subsequent high-temperature grade doping region drive-in.
Moreover, fence defect is found at the boundary between the high-voltage device area and the low-voltage device area after the definition and etching of polysilicon gates. This is because the poly gate for the high-voltage devices and poly gate of the low-voltage devices are defined by using two photo masks according to the prior art.